Pass 2.3

[Boehm, Hans]

I think that for all modern workstation and server class processors,
aligned byte, 2-byte, 4-byte, and pointer-sized updates are done
with store instructions that specify the width and appear atomic.
The actual bus transaction is cache-line sized, but the hardware
does enough magic that you can't tell.  That applies for both RISC
and CISC machines, though X86 supports unaligned operations, which
are not atomic, but also don't rewrite adjacent memory.

But for this iteration, I think it doesn't matter.


Hans



> -----Original Message-----
> From: Andrei Alexandrescu [mailto:andrei at metalanguage.com]
> Sent: Saturday, September 11, 2004 6:00 PM
> To: Doug Lea
> Cc: Boehm, Hans; Kevlin Henney; Doug Lea; 'Ben Hutchings';
> pugh at cs.umd.edu
> Subject: Re: Pass 2.3
> 
> 
> I now start feeling sorry for having added that paragraph :o).
> 
> I thought this is a more widespread problem. Basically 
> reading a full word,
> masking, and writing a word is how all RISCs do byte-level 
> updates. Now the
> question is if that's atomic or not. My suspicion was that (1) some
> processors choose the faster path to make atomicity an 
> option, and (2) some
> compilers know that non-atomic is slower so they generate 
> three instructions
> to do things "by hand" if they assume single-threading.
> 
> Likely I was wrong. I now am sorry about adding a not-so-relevant
> paragraph...
> 
> 
> Andrei
> 
> ----- Original Message ----- 
> From: "Hans Boehm" <Hans.Boehm at hp.com>
> To: "Doug Lea" <dl at cs.oswego.edu>
> Cc: "Boehm, Hans" <hans.boehm at hp.com>; "'Andrei Alexandrescu'"
> <andrei at metalanguage.com>; "Kevlin Henney" 
> <kevlin at curbralan.com>; "Doug
> Lea" <dl at altair.cs.oswego.edu>; "'Ben Hutchings'"
> <ben at decadentplace.org.uk>; <pugh at cs.umd.edu>
> Sent: Saturday, September 11, 2004 12:52 PM
> Subject: RE: Pass 2.3
> 
> 
> > On Sat, 11 Sep 2004, Doug Lea wrote:
> >>
> >> I probably also should have mentioned that on most small embedded
> >> systems you can just disable interrupts etc to emulate atomics. (I
> >> suppose it is implicit though in that this is also how some of them
> >> implement locks.)
> > Good point.  However, I think a dual core ARM was announced 
> recently,
> > so this may stop working for some "bare metal" embedded 
> applications.
> >>
> >>
> >> > I'm still not sure there are actually important 
> architectures with the
> >> > problem you mention below.  It is something to look at, though.
> >>
> >> I believe the Alpha had this problem. Even if alphas never 
> meet next
> >> C++ standard, probably some processor designer will 
> someday decide to
> >> also make a chip with word-tearing problems.
> >>
> > For Alphas, I think this was fixed a long time ago.  I 
> personally think
> > that we don't have to accomodate future mistakes in this 
> area.  If someone
> > designs a multiprocessor with this sort of issue, they get what they
> > deserve.
> >
> > Hans
> >
>