[cpp-threads] memory model

[Alexander Terekhov]

On 5/1/05, Peter Dimov <pdimov at mmltd.net> wrote:
[...]
> In Sparc-like terms, load_acq is
> 
>    load
>    #LoadLoad | #LoadStore

(Just for the sake of completeness)

load_hlb is

   load
   #LoadLoad 

load_hsb is

   load
   #LoadStore

> 
> load_ccacq is
> 
>    load
>    #LoadLoad

load_cchlb is

   load
   #LoadLoad 

load_cchsb is

   load

> 
> because control-dependent stores are implicitly ordered, and load_ddacq is
> 
>    load

same for load_ddhlb and load_ddhsb.

> 
> because data-dependent accesses are implicitly ordered.
> 
> (I hope I got these right.)

Likewise. 

Note that "emulation" of acq stuff with trailing bidirection 
Spac-like fences still orders way too much so to speak. "Ideal" 
hardware would provide Itanic-like unidirectional labels, but 
would also allow naked "semaphore" stuff and hlb-only/hsb-only 
relaxation (in addition to classic acquire), and would also 
have labels for constituent sink barriers of classic release.

regards,
alexander.