[cpp-threads] [Fwd: [Javamemorymodel-discussion] MSDN onMemorymodels]

[Boehm, Hans]

> From: Alexander Terekhov
> Sent: Tuesday, September 13, 2005 5:44 PM
> To: cpp-threads at decadentplace.org.uk
> Subject: Re: [cpp-threads] [Fwd: [Javamemorymodel-discussion] 
> MSDN onMemorymodels]
> 
> 
> On 9/14/05, Boehm, Hans <hans.boehm at hp.com> wrote:
> [...]
> > current SPARC TSO) either, but I don't understand it well enough
> 
> SPARC TSO == IA32-under-IA64/WB == IA32-native/WB + "remote 
> write atomicity". Apart from a few minor details.
> 
> See also (TSO vs processor consistency):
> 
> http://research.compaq.com/wrl/people/kourosh/papers/1995_thesis.pdf

That agrees with my understanding of the memory model.  But there may
well also be a difference between in-order and out-of-order instruction
issue here, that I was alluding to.  My understanding is that current
SPARC implementations rely heavily on compiler instruction scheduling
(as do current IA64 implementations).  In my experience, most modern X86
implementations are only minimally sensitive to that.  Independent of
any memory fence issues, there's a question of how much it costs to
prevent the compiler from reordering writes.  It's certainly greater for
in-order processors.  But I actually don't have a very good feeling for
the costs.  Does anyone else on this list?


Hans