[cpp-threads] Causality on more than two processors, write atomicity

[Hans Boehm]

I was just rereading this thread, and I can't quite make sense out of some
things.  It seems to me that if Peter's example were Java code, and all
variables were volatile, by the usual guidelines we have been giving
everyone, no barriers are needed on X86, since there are no stores
followed by loads, right?

But operations on Java volatiles are totally ordered, so Y != 0 in P1
should be impossible, right?

What, if anything, am I missing?

Hans

On Sat, 3 Sep 2005, Peter Dimov wrote:

> There is a discussion in comp.programming.threads, in which the following
> example:
>
> P1: Y = 1;
> P2: if( Y == 1 ) { Z = 1; }
> P3: if( Z == 1 ) { assert( Y == 1 ); }
>
> is claimed to legitimately assert under "processor consistency" - the memory
> model that the x86 CPUs are supposed to implement, and under all platforms
> that don't exhibit write atomicity (even when all loads are ld.acq and all
> stores are st.rel).
>
> I'm still struggling with this "discovery". How does it affect us? It seems
> to me that this makes ld.acq/st.rel impossible to specify in a
> happens-before framework (because in the above example happens-before is not
> transitive.) I must be missing something.
>
> --
> Peter Dimov
> http://www.pdimov.com
>
>
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