[cpp-threads] Re: A hopefully clearer document on POSIX threads

[Herb Sutter]

Jumping in quickly, just hit me on the head if I'm missing context and
this is off point:

Nick wrote, quoting Hans:
> > Don't we need to guarantee the CPU cache coherency across all
> > the CPU's?
> I think this is getting a bit off topic, but ...
> 
> The machines we're directly addressing are all cache-coherent, i.e.
the
> hardware assures that all the caches are consistent.  Typically this
> means that a machine can only update a cache line after acquiring
> exclusive ownership of the line, thus ensuring it is cached nowhere
> else.
> 
> This does not ensure sequential consistency since, for example, all
> modern processors contain a store buffer, and thus stores appear to
> complete, and the result becomes locally visible, before the value
makes
> it into the cache, or becomes visible to other processors.

But what about the causality example raised some months ago here? In
particular:

  initial: x = y = 0;

  P0: x = 1;

  P1: if( x == 1 ) y = 1;

  P2: if( y == 1 ) assert ( x == 1 ); // can P2 see y==1 before x==1?

I am told by Intel that they are undecided about whether/how this works
both on current IA32/IA64 SMP systems and on medium-term IA32/IA64 4+
core CMP systems (i.e., whether it is guaranteed at all, and if so what
fences or other operations you'd have to emit to force it to work). In
particular, if P0/P1 have a shared cache and x=1 could become visible to
P1 before P2, and then the y=1 and x=1 updates could become visible to
P2 in that order.

Herb