[cpp-threads] RE: "Agenda" for august 23-25 concurrency meeting

[Alexander Terekhov]

On 9/1/06, Doug Lea <dl at cs.oswego.edu> wrote:
> Robison, Arch wrote:
> > TBB's atomic operations support only relaxed consistency.  In the cited

Which relaxed consistency? There are many.

> > archive thread
> > http://www.decadentplace.org.uk/pipermail/cpp-threads/2005-September/000
> > 610.html, Doug Lea notes:
> >
> >> And historically, almost no algorithms/programs have ever been
> >> found to require such strong guarantees. We once challenged
> >> people to come up with non-toy examples, and never got any.
> >
> > If you have a non-toy example algorithm that shows a need for causality
> > or total store order, I would very much like to see it and show it to
> > our hardware architects.
> >
>
> Despite lack of a killer example,

Assume PC (or RCpc) hardware.

atomic<Y *> pY(0);
atomic< Z *> pZ(0);

P1: pY.store_rel(new Y("lazy init"));
P2: if (Y * p = pY.load_acq()) pZ.store_rel(new Z(p->f()));
P3: if (Z * p = pZ.load_acq()) p->f(pY.load_acq()->g());

UB in P3 is quite a killer. It can go boom on IA32-native (allegedly
PC). IA64 and IA32-under-IA64 is safe (for WB), however.

IA32-native (and Power/PPC) friendly solution:

P3: if (Z * p = pZ.load_acq()) p->f(pY.load_acq<TSO>()->g());

with dummy RMW ensuring illusion of TSO for pY.load_acq.

regards,
alexander.