[cpp-threads] RE: "Agenda" for august 23-25 concurrency meeting

[Robison, Arch]

Alexander Terekhov wrote:
> Talk to your Itanium architects. For some reason, they imposed remote
> write atomicity for release stores to WB memory (total store order for
> Itanium "semaphores"). There must be something that they had in mind
> to justify this restriction, I suppose.

I asked around, and got many helpful insights.  Here's a summary,
speaking as an informal historian, not as official Intel position.
Itanium was designed back in the 1990s, the cambrian age for memory
models where many different memory models flowered on various machines.
The performance difference between causality and total store order (TSO)
was thought to be small for Itanium because most writes on Itanium are
ordinary writes, which follow more relaxed rules.  The Itanium
architects considered causality important, but hard to explain.  Total
store order guaranteed causality, and was easy to explain.  Hence TSO
for atomic operations offered a good tradeoff of performance and
programming simplicity.  

Doug Lea wrote:
> Despite lack of a killer example, and my belief that macho
> lock-free programmers could cope with lack of guaranteed
> transitivity, I am still uncomfortable about
> relaxing requirements for TSO-ness as a both a human-factors
> and language semantics concern.

I agree that transitivity (causality) is important, but I think it
premature to require the stronger guarantee of TSO.  With multi-core and
multi-threaded cores, architectures seem to be undergoing a second
cambrian explosion, and not all the tradeoffs are fully understood. 

- Arch Robison