[cpp-threads] A niggle on the atomic model (N2145)

Boehm, Hans hans.boehm at hp.com
Tue Apr 24 01:20:35 BST 2007


> -----Original Message-----
> From: cpp-threads-bounces at decadentplace.org.uk 
> [mailto:cpp-threads-bounces at decadentplace.org.uk] On Behalf 
> Of Nick Maclaren
> Sent: Saturday, April 21, 2007 12:21 PM
> To: C++ threads standardisation
> Cc: lawrence at crowl.org
> Subject: Re: [cpp-threads] A niggle on the atomic model (N2145) 
> 
> Well, my copy of the Alpha architecture says at the end of 4-12:
> 
>     Although this is not recommended, the address specified by a STx_C
>     instruction need not match that given by a preceding 
> LDx_L.  Further,
>     specifying unmatched addresses for those instructions requires an
>     MB in between to guarantee ordering.
The one I just downloaded states:

"If the virtual and physical addresses for a LDx_L and STx_C sequence
are not within
the same naturally aligned 16-byte sections of virtual and physical
memory, that
sequence may always fail, or may succeed despite another processor's
store to the lock
range; hence, no useful program should do this."

That's what I would have expected.

> 
> PLEASE specify that mapping the same physical location to two 
> virtual ones is undefined.  We may not see virtual caches or 
> Alpha style LDx_L/STx_C come back, but encouraging users to 
> write code that depends on them not doing so is asking for trouble.
I'm not sure we actually have any direct control over this, since I
don't believe it's possible to create such mappings in a pure C++
program.  I think Posix, as an important example, currently doesn't
prohibit it.

Since we're only talking about single location atomic operations, I'm
still not completely sure whether anything at the C++ level breaks
unexpectedly.  But I think we're not promising anything to start with.

Hans

> 
> Also, I would HATE to have to emulate a physical cache in 
> software; it might be possible, but I require notice of that question.
> 
> 
> Regards,
> Nick Maclaren,
> University of Cambridge Computing Service, New Museums Site, 
> Pembroke Street, Cambridge CB2 3QH, England.
> Email:  nmm1 at cam.ac.uk
> Tel.:  +44 1223 334761    Fax:  +44 1223 334679
> 
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