[cpp-threads] Re: Increment/decrement operators on atomics package

[Raul Silvera]

cpp-threads-bounces at decadentplace.org.uk wrote on 04/27/2007 06:27:13 PM:

> On 4/27/07, Raul Silvera <rauls at ca.ibm.com> wrote:
> [...]
> > > on an atomic<> would effectively be a RMW? (Remote write atomicity,
IRIW
> > > and all that...)
> >
> > No. Part of the argument during the SC discussion was RMW operations
> > wouldn't be needed to implement SC memory accesses, so that loads would
be
> > relatively cheap.
> [...]
> > Particularly for PPC, SC only requires fences between each pair of
memory
> > accesses,
>
> Earlier you said that this is still being debated inside IBM.

At this point we're fairly confident that SC is achievable on current PPC
implementations by having hwsyncs between each pair of accesses. It is
widely believed that this was the intent of the architecture, and this is
supported by some interpretations of the current text on Book II.

> Is the updated Book II publicly available?

I don't know if there will be an updated Book II to clarify this issue.

--
Raúl E. Silvera         IBM Toronto Lab   Team Lead, Toronto Portable
Optimizer (TPO)
Tel: 905-413-4188 T/L: 969-4188           Fax: 905-413-4854
D2/KC9/8200/MKM