[cpp-threads] Relaxed reload example

[Herb Sutter]

Sarita wrote:
> Another way this could happen in hardware is if the release barriers
> only ensure that invalidations are posted at other processors and
> acquire side barriers ensure that all posted invalidates actually affect
> their processor's cache. Then the said outcome can occur if the
> dereferenced address is cached and the invalidation isn't yet applied to
> the cached copy (because there is no memory barrier). There is no
> speculation here.

Yes, that's exactly the scenario the original person had in mind when posting the question.

Herb