[cpp-threads] A question about N2153

[Raul Silvera]

cpp-threads-bounces at decadentplace.org.uk wrote on 01/30/2007 03:36:07 PM:

> Raul Silvera wrote:
>
> > Yes. I think that anything else couldn't really be called ordered.
> > On PPC, it would require a leading sync and a trailing lwsync.
> >
> > In most cases, the useful variant is the acquire RMW, which will be
> > just a trailing isync.
>
> I'm still not 100% sure that I understand the (formal) RMW semantics WRT
> memory ordering. Question:
>
> // x y initially 0
>
> // thread 1
>
> fetchadd_acquire( &x, +1 );
> r1 = load_raw( &y );
>
> // thread 2
>
> fetchadd_acquire( &y, +1 );
> r2 = load_raw( &x );
>
> Is r1,r2 == 0,0 possible?

No, as currently defined it is not possible. And I do see your point that a
trailing isync wouldn't be sufficient to guarantee that.
It was the intent to define it in a way that would now require a StoreLoad
barrier, though. So, a corrected definition would require only the load
part of the RMW operation to be affected by the ordering constraints.

Thanks for pointing this out.