[cpp-threads] Web site updated

[Peter Dimov]

Paul E. McKenney wrote:

>> Similarly, I'd expect in
>>
>> a.store_raw( 5 );
>> a.store_raw( 6 );
>>
>> the first store to be optimized out.
>
> MMIO accesses, anyone?

This is what volatile is for.

> Hardware timing analysis (especially if there is a short loop between the 
> two)?

(1) A short loop composed of ordinary operations can be reordered across 
either store;
(2) Only volatiles are "observable behavior". The compiler is not required 
to care about timing on nonvolatiles, or it would be able to perform no 
optimization at all.