[cpp-threads] Alternatives to SC

[Alexander Terekhov]

On 1/16/07, Raul Silvera <rauls at ca.ibm.com> wrote:
[...]
> > A sync()-less version with lwarx/stwcx loop on P3 relies on implicit
> > ordering of stores by control dependencies (code conditional hoist
> > store barrier implied by hardware) and ability of stwcx to detect
> > "stale" values loaded by lwarx.
>
> Oh, I understand what you're proposing now. You're relying on the control
> flow dependence ordering the load of y and an invented stwcx x that you
> would introduce with the same value you loaded from x.
>
> As clever as that is, it is overkill (plus not general: for all P3 knows, x
> could be on read-only memory). PPC will order loads vs control-flow
> dependent loads as long as there is an isync after the conditional branch.
> For this example, I believe the minimum synchronization required would be:
>
> > > > > P1: x = 1;
> > > > > P2: if (x == 1) lwsync(), y = 2;
> > > > > P3: if (y == 2) isync(), assert(x == 1);
>
> Note that P2 only needs an lwsync because it is ordering a load and a
> store,

For mere ordering of load x and store y on P2, lwsync is not needed --
see "B.2.3 Safe Fetch" in Book II.

> and P3 only needs an isync because we're relying on the control-flow
> dependence

Well, lwarx-stwcx-on-P3 version aside for a moment, at least one
"cumulative" barrier is needed on P2/P3 (Book II shows two) I think.

Ordering and visibility on Power is rather murky, isn't it? ;-)

regards,
alexander.