[cpp-threads] A question about N2153

[Peter Dimov]

Raul Silvera wrote:

>> On 1/23/07, Raul Silvera <rauls at ca.ibm.com> wrote:
>>> As per the definitions in N2153, an ordered RMW has the acquire and
>>> release orderings apply to both the load and store implied by the
>>> operation.
>>
>> Do you really want to impose no less than sync on both sides of LR-SC
>> on Power (leading lwsync + trailing isync won't do it)?
>>
>> regards,
>> alexander.

> Yes. I think that anything else couldn't really be called ordered.
> On PPC, it would require a leading sync and a trailing lwsync.
>
> In most cases, the useful variant is the acquire RMW, which will be
> just a trailing isync.

I'm still not 100% sure that I understand the (formal) RMW semantics WRT 
memory ordering. Question:

// x y initially 0

// thread 1

fetchadd_acquire( &x, +1 );
r1 = load_raw( &y );

// thread 2

fetchadd_acquire( &y, +1 );
r2 = load_raw( &x );

Is r1,r2 == 0,0 possible?