[cpp-threads] Implicit Conversion for Atomics

[Raul Silvera]

Hans wrote on 01/28/2008 08:58:39 PM:

> [image removed]
>
> Re: [cpp-threads] Implicit Conversion for Atomics
>
> > On 1/22/08, Peter Dimov <pdimov at mmltd.net> wrote:
> > > > In the October 2007 C++ meeting in Kona, I agreed to write up a
> > > > paper on the issues with implicit conversion operators on
> > the atomic
> > > > types.  My first draft is attached.
> > >
> > > You state in the "hides cost" section that
> > >
> > >     An atomic store is generally more expensive than an atomic load.
> > >
> > > Is this indeed true for the seq_cst constraint?
> >
> > Good question.  I don't have an immediate answer.
> >
> It's pretty clearly true on X86 (at least in the absence of SSE,
> which we still need to understand more completely).  The canonical
> implementation of SC atomics there is
>
> store -> xchg (includes a fence)
> load -> ordinary load (actually mov)
>
> On Itanium, this is also true:
> store -> st.rel; mf
> load -> ld.acq
>
> On ARM, there isn't much of a difference, though my impression is
> that fences are relatively cheap, so this isn't a huge deal.
>
> On PowerPC, my impression is that they each include a trailing heavy
> weight sync, but the store also needs a leading lwsync.  The
> difference probably isn't huge.
>
> Hans
>

I believe SC stores can be implemented on PPC without a trailing *sync. So
we only need to associate an expensive heavyweight sync to the loads.

So it seems to me that PPC is the exception here, where SC loads have
associated to them a more expensive synchronization cost than SC stores.

--
Raúl E. Silvera         IBM Toronto Lab   Team Lead, Toronto Portable
Optimizer (TPO)
Tel: 905-413-4188 T/L: 969-4188           Fax: 905-413-4854
D2/KC9/8200/MKM