[cpp-threads] std::atomic<> in acquire-release mode and write atomicity

[Paul E. McKenney]

On Tue, Dec 16, 2008 at 02:46:32AM +0100, Alexander Terekhov wrote:
> On Tue, Dec 16, 2008 at 1:00 AM, Paul E. McKenney
> <paulmck at linux.vnet.ibm.com> wrote:
> [...]
> > I agree that std::atomic<> in acquire-release mode does not support IRIW.
> > Whether this is due to a failure to totally order stores or a failure
> > to provide cumulativity to loads is a philosophical point, at least from
> > what I can tell.  ;-)
> 
> How about
> 
> P1: Y = 1;
> P2: if( Y == 1 ) { Z = 1; }
> P3: if( Z == 1 ) { assert( Y == 1 ); }
> 
> ?

Hmmm...  No memory fences of any kind, so that the loads and stores
are all memory_order_relaxed, correct?  If so:

o	On P2, the store to Z will not be performed with respect to
	any processor until after the load from Y has been performed
	with respect to all processors, since PowerPC forbids
	speculative stores.  (More accurately, PowerPC allows the
	store -instruction- to be speculated, but not the resulting
	store -operation- to memory.  See section 4.2.4 of PowerPC
	Book 3.)

o	On P3, there is nothing preventing the load from Y from being
	reordered to precede the load from Z, as there is no data
	dependency between them, and because there is no "isync"
	instruction between them.

So I believe that this assertion can fail on PowerPC, but if you really
care about the answer, I should run it by a few PowerPC experts.

							Thanx, Paul