[cpp-threads] Brief tentative example x86 Implementation for C/C++Memory Model

[Alexander Terekhov]

On Fri, Dec 26, 2008 at 6:11 PM, Peter Dimov <pdimov at mmltd.net> wrote:
>> Seq_Cst Fence: MFENCE
>
> I think that this is not yet officially guaranteed by Intel or AMD; I could
> find no definite statement on whether MFENCE instructions form a total
> order. A conservative implementation might opt to use a dummy LOCKed
> instruction instead.

Okay. (See my reply regarding the issue of store-load fencing and Load
Acquire in "ITANIUM Implementation" thread.)

Load Relaxed:  MOV (from memory)
Load Consume:  MOV (from memory)
Load Acquire:  MOV (from memory)
Load Seq_Cst:  LOCK XADD(0) // alternative: MFENCE,MOV (from memory)
Store Relaxed: MOV (into memory)
Store Release: MOV (into memory)
Store Seq Cst: LOCK XCHG    // alternative: MOV (into memory),MFENCE
Consume Fence: <ignore>
Acquire Fence: <ignore>
Release Fence: <ignore>
Acq_Rel Fence: <ignore>
Seq_Cst Fence: LOCK XCHG(dummy) // alternative: MFENCE

regards,
alexander.