[cpp-threads] Brief example ARM Implementation for C/C++ Memory Model

[Alexander Terekhov]

(cmpxchg aside for a moment)

Load Relaxed:  LDR
Load Consume:  LDR
Load Acquire:  LDR, DMB
Load Seq_Cst:  DMB,LDR,DMB
Store Relaxed: STR
Store Release: DMB,STR
Store Seq Cst: DMB,STR,DMB
Consume Fence: <ignore>
Acquire Fence: DMB
Release Fence: DMB
Acq_Rel Fence: DMB
Seq_Cst Fence: DMB

Any objections and/or questions?

TIA.

regards,
alexander.