[cpp-threads] Brief example ARM Implementation for C/C++ Memory Model

[Hans Boehm]

Except for sequentually consistent loads, this is consistent with my 
understanding.  Thanks for posting these.

There is also a very rough introduction to implementation considerations
in my "Threads Basics" paper at

http://www.hpl.hp.com/personal/Hans_Boehm/c++mm/threadsintro.html

but this focusses almost entirely on the "sequentially consistent for drf"
subset, and is much less specific.  Doug Lea's Java JSR133 cookbook
at http://g.oswego.edu/dl/jmm/cookbook.html also effectively covers this
subset in more detail.

Hans

On Sat, 27 Dec 2008, Alexander Terekhov wrote:

> (cmpxchg aside for a moment)
>
> Load Relaxed:  LDR
> Load Consume:  LDR
> Load Acquire:  LDR, DMB
> Load Seq_Cst:  DMB,LDR,DMB
> Store Relaxed: STR
> Store Release: DMB,STR
> Store Seq Cst: DMB,STR,DMB
> Consume Fence: <ignore>
> Acquire Fence: DMB
> Release Fence: DMB
> Acq_Rel Fence: DMB
> Seq_Cst Fence: DMB
>
> Any objections and/or questions?
>
> TIA.
>
> regards,
> alexander.
>
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