[cpp-threads] modes, pass 2

[Doug Lea]

This is mostly off-topic but...

> 
> http://web.archive.org/web/20030529104801/http://www.cs.umd.edu/~pugh/java/memoryModel/archive/1220.html
> (ExitEnter...)
> 
> Perhaps it's time for you to answer/elaborate. ;-)

Presumably you mean ...

> Now, with respect to PowerPC... The cookbook says that isync
> is a LoadLoad barrier. I don't think so. To the best of my
> knowledge, the isync instruction can be used to build a sort
> of "PowerPC version" of IA64's cmpxchg.acq with post-LoadLoad
> (and post-LoadStore? please see the question above), but on
> its own (without some "branch instruction that depends on the
> value returned by a preceding Load instruction" -- pls see the
> Book-E), it can NOT be used as LoadLoad barrier. The Book-E
> actually says: "The isync instruction may complete before
> storage accesses associated with instructions preceding the
> isync instruction have been performed." 

Every time a question like this has arisen about PPC, I have asked
people at IBM. And I generally revise cookbook with the answers I get,
which have not always been consistent. I keep thinking that I should
just kill all mention of PPC rather than try to take responsibility for 
it. If anyone would like to help collect the authoritative answers here,
please feel free to help me out!

Two notes on it though.

1. Apparently no PPC exactly implements Book-E. Including Power5.

2. The semantics of eieio and isync might be different on different
    versions of PPC.

-Doug