[cpp-threads] modes, pass 2

[Alexander Terekhov]

On 5/9/05, Doug Lea <dl at cs.oswego.edu> wrote:
> 
> This is mostly off-topic but...
> 
> >
> > http://web.archive.org/web/20030529104801/http://www.cs.umd.edu/~pugh/java/memoryModel/archive/1220.html
> > (ExitEnter...)
> >
> > Perhaps it's time for you to answer/elaborate. ;-)
> 
> Presumably you mean ...
> 
> > Now, with respect to PowerPC... 

No. I mean

----
"However, an ExitEnter (StoreLoad) barrier is in general still 
 needed between successive MonitorExits and MonitorEnters. " 

Why is an extra StoreLoad barrier needed between successive 
MonitorExits and MonitorEnters via cmpxchg.rel/acq? Would 
someone please elaborate? 

Well, I did noticed the following: 

"ExitEnter is needed between (dynamically) successive 
 synchronized blocks or methods to properly deal with code in 
 which one thread does: 

   synchronized(x) { x.afield = 1; } 
   ... 
   synchronized(x) { int i = x.afield; } 

 and another does: 

   synchronized(x) { x.afield = 2; } 
   ... 
   synchronized(x) { int i = x.afield; } 

 ExitEnter is the same as StoreLoad unless atomic instructions 
 are used in MonitorExit and/or MonitorEnter and at least one 
 of these provide a barrier with at least the properties of 
 StoreLoad, in which case it is a no-op. " 

But I don't quite understand what's the problem here. :-( 
----

[...]
> > Book-E), it can NOT be used as LoadLoad barrier. The Book-E
> > actually says: "The isync instruction may complete before
> > storage accesses associated with instructions preceding the
> > isync instruction have been performed."
> 
> Every time a question like this has arisen about PPC, I have asked
> people at IBM. And I generally revise cookbook with the answers I get,
> which have not always been consistent. I keep thinking that I should
> just kill all mention of PPC rather than try to take responsibility for
> it. If anyone would like to help collect the authoritative answers here,
> please feel free to help me out!

No comment. ;-) Well, but if you have access to IBM's w3forums, see my 
"PMFJI" message in "Apparent memory consistency in SMP Power5 
environment" thread at forums.hardware.powerpc...

> 
> Two notes on it though.
> 
> 1. Apparently no PPC exactly implements Book-E. Including Power5.

Well, the passage that I quoted can be found in

http://www-106.ibm.com/developerworks/eserver/pdfs/archpub2.pdf

as well.

> 
> 2. The semantics of eieio and isync might be different on different
>    versions of PPC.

Hopefully not (as far as arch spec is concerned).

regards,
alexander.