[cpp-threads] modes, pass 2

[Doug Lea]

> 
> No. I mean
> 
> ----
> "However, an ExitEnter (StoreLoad) barrier is in general still 
>  needed between successive MonitorExits and MonitorEnters. " 

The underlying need here is (of course) for at least one StoreLoad
between a lock release and a lock acquire.
I should revise that passage because the example doesn't
illustrate the intended issue -- that If you don't know for sure you
have it on one side, you need it on the other side.
So the "in general" disclaimer covers only those cases
where you don't know if a lock has been used correctly
(i.e., the monitorEnter/monitorExits aren't properly nested)
which is (as of JVMS spec v2) not even legal.

>>
>>Every time a question like this has arisen about PPC, I have asked
>>people at IBM. And I generally revise cookbook with the answers I get,
>>which have not always been consistent. I keep thinking that I should
>>just kill all mention of PPC rather than try to take responsibility for
>>it. If anyone would like to help collect the authoritative answers here,
>>please feel free to help me out!
> 
> 
> No comment. ;-) Well, but if you have access to IBM's w3forums, see my 
> "PMFJI" message in "Apparent memory consistency in SMP Power5 
> environment" thread at forums.hardware.powerpc...
> 

I don't think I do.
If you think it would help clear things up for the (many!) people
who read cookbook, could you please ask permission to send
me whatever clarifications this entails?

-Doug