[cpp-threads] RE: "Agenda" for august 23-25 concurrency meeting

[Robison, Arch]

TBB's atomic operations support only relaxed consistency.  In the cited
archive thread
http://www.decadentplace.org.uk/pipermail/cpp-threads/2005-September/000
610.html, Doug Lea notes:

> And historically, almost no algorithms/programs have ever been
> found to require such strong guarantees. We once challenged
> people to come up with non-toy examples, and never got any.

If you have a non-toy example algorithm that shows a need for causality
or total store order, I would very much like to see it and show it to
our hardware architects.  

Alexander Terekhov" <alexander.terekhov at gmail.com> wrote:
> On 8/30/06, Nick Maclaren <nmm1 at cus.cam.ac.uk> wrote:
> > "Alexander Terekhov" <alexander.terekhov at gmail.com> wrote:
...
> > > I've got one simple question. How one is supposed to do classic SC
> > > (Lamport's) on IA-32 multi (core/processor/HT/whatever)?
...
> It's regarding "6.2 atomic< T > Template Class". I'm after "remote
> write atomicity". On MP, a store is actually a bunch of stores with
> respect to other processors. Under classic SC, this whole bunch is
> atomic. Under PC (processor consistency), it is not.. unless your
> reads are dummy RMWs, e.g. ia32_lock_cmpxchg(&var, 42, 42).
>
>
http://www.decadentplace.org.uk/pipermail/cpp-threads/2005-September/000
610.html
>
> See the entire thread.

- Arch Robison