[cpp-threads] RE: "Agenda" for august 23-25 concurrency meeting

[Alexander Terekhov]

On 8/30/06, Nick Maclaren <nmm1 at cus.cam.ac.uk> wrote:
> "Alexander Terekhov" <alexander.terekhov at gmail.com> wrote:
> > On 8/29/06, Robison, Arch <arch.robison at intel.com> wrote:
> > > The Intel(R) Threading Building Blocks that I presented at the meeting
> > > is now an official product, so anyone can download the documentation
> > > from: http://www3.intel.com/cd/software/products/asmo-na/eng/294796.htm
> >
> > I've got one simple question. How one is supposed to do classic SC
> > (Lamport's) on IA-32 multi (core/processor/HT/whatever)?
>
> Eh?  Can you explain?

It's regarding "6.2 atomic< T > Template Class". I'm after "remote
write atomicity". On MP, a store is actually a bunch of stores with
respect to other processors. Under classic SC, this whole bunch is
atomic. Under PC (processor consistency), it is not.. unless your
reads are dummy RMWs, e.g. ia32_lock_cmpxchg(&var, 42, 42).

http://www.decadentplace.org.uk/pipermail/cpp-threads/2005-September/000610.html

See the entire thread.

regards,
alexander.