[cpp-threads] SC on PPC (was Re: Increment/decrement operators onatomics package)

[Alexander Terekhov]

On 4/30/07, Peter Dimov <pdimov at mmltd.net> wrote:
> Raul Silvera wrote:
> > Alexander Terekhov wrote on 04/30/2007 08:10:19 AM:
> >
> >> How does cumulativity help in the IRIW case?
> >>
> >> P1: x = 1;
> >> P2: y = 1;
> >> P3: r1 = x; r2 = y;
> >> P4: r3 = y; r4 = x;
> >>
> >
> > The short version of this is that cumulativity on a hwsync between
> > the two loads on P3 would cause a StoreLoad ordering between P1's
> > store to x and P3's load of y.
>
> Interesting. Does this mean that an ordered load is
>
> sync
> load
> sync
>
> and not
>
> sync
> load
> lwsync
>
> as I assumed at first? (Under a context-free literal translation.)
>
> I think that we need a "cookbook" on how to implement the various
> constraints on PPC, x86, IA64, SPARC TSO, and possibly ARM.

In my "cookbook" an ordered load on PPC is

sync
lr-sc loop
isync

regards,
alexander.