[cpp-threads] SC on PPC

[Raul Silvera]

Alexander Terekhov  wrote on 04/30/2007 03:09:12 PM:

> On 4/30/07, Raul Silvera <rauls at ca.ibm.com> wrote:
> >
> > Alexander Terekhov wrote on 04/30/2007 08:10:19 AM:
> >
> > > How does cumulativity help in the IRIW case?
> > >
> > > P1: x = 1;
> > > P2: y = 1;
> > > P3: r1 = x; r2 = y;
> > > P4: r3 = y; r4 = x;
> > >
> >
> > The short version of this is that cumulativity on a hwsync between the
two
> > loads on P3 would cause a StoreLoad ordering between P1's store to x
> > and P3's load of y.
>
> This is rather intriguing because unless I'm just missing something,
> cumulativity is defined the same for all barriers including
> lwsync/eieio and it comes into play when *P3* makes a post-barrier
> store which is observed by another processor.

There are two components to cumulativity. What you're describing is what
we call B-cumulativity, which extends the B set with loads that observe
a store in B. What you're missing is A-cumulativity, which extends the
A set with operations that were performed before the barrier with respect
to the current processor. This is all spelled out in Book II.

> >
> > Do the same for P4, plus some wild hand-waving, and you get to forbid
the
> > disallowed IRIW outcome.
>
> That's a lot of hand-waving, I'm afraid. ;-)

I sort of agree. It has to do with transitivity of operations, and this is
why I said before that it is supported by "some interpretations" of the
current text. There is certainly no text on Book II that explicitly spells
out how to achieve SC.

--
Raúl E. Silvera         IBM Toronto Lab   Team Lead, Toronto Portable
Optimizer (TPO)
Tel: 905-413-4188 T/L: 969-4188           Fax: 905-413-4854
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