[cpp-threads] Yet another visibility question

[Peter Dimov]

Hans Boehm wrote:

> Once you fix the bug in the example by inverting the two loads in
> threads 4, the answer is yes, I would like that.  (As written, this
> is possible in an SC execution.)

Oops. :-)

> There are also those people who
> feel we're not going to get it.  But I think the verdict is still out.
>
> There are still parallel discussions about hardware implications, and
> how difficult this really is on existing hardware, as opposed to with
> existing hardware specs, to what extent it inherently slows down
> the hardware, and whether or not we can actually describe the
> semantics of atomics intelligibly without this property.

I'm still a bit confused. N2145 doesn't contain any support for sequential 
consistency, does it? I recall that when I suggested that we need 
atomic_op_fence to support SC, nobody seemed to like this addition, and 
_ordered was specifically not intended to deliver SC. Right?

If the plan is to support SC only in atomic<> and not in the low-level 
layer, do we have an idea how this is going to be implemented? Maybe just do 
what Java does? Are we sure that the existing Java implementations ensure a 
total system-wide order of all volatile stores? The cookbook makes no 
mention of that and implies that no barriers are needed in my example under 
x86. But x86 is not TSO, is it?