[cpp-threads] Yet another visibility question

[Alexander Terekhov]

On 1/11/07, Hans Boehm <Hans.Boehm at hp.com> wrote:

[... Peter: "x86. But x86 is not TSO, is it?" ...]

> Some of these issues were not fully understood when the Java memory model
> was agreed upon either.  It is not completely clear to me to what extent
> current X86 implementations are TSO;

http://arxiv.org/pdf/cs.AR/0605039.pdf

"The algorithm assumes store atomicity, which is necessary for Axiom 3.
However it supports slightly relaxed consistency models which allow a
load to observe a local store which precedes it in program order,
before it is globally observed. Thus we cover all coherence protocols
that support the notion of relaxed write atomicity which can be defined
as: No store is visible to any other processor before the execution
point of the store. Based on our discussion with Intel microarchitects
we determined that all IA-32 and current generations of Itanium
microprocessors support this due to identifiable and atomic global
observation points for any store. This is mostly due to the shared bus
and single chipset."

regards,
alexander.