[cpp-threads] Yet another visibility question

[Peter Dimov]

Alexander Terekhov wrote:

[...]

> can be defined as: No store is visible to any other processor before
> the execution point of the store. Based on our discussion with Intel
> microarchitects we determined that all IA-32 and current generations
> of Itanium microprocessors support this due to identifiable and
> atomic global observation points for any store. This is mostly due to
> the shared bus and single chipset."

It's my understanding that AMD Opterons have a separate memory controller 
per socket; no shared bus and no single chipset (north bridge). They are 
also NUMA since some parts of the memory are attached to this CPU and some 
require CPU to CPU communication.