[cpp-threads] Yet another visibility question

[Alexander Terekhov]

On 1/11/07, Peter Dimov <pdimov at mmltd.net> wrote:
> Alexander Terekhov wrote:
>
> [...]
>
> > can be defined as: No store is visible to any other processor before
> > the execution point of the store. Based on our discussion with Intel
> > microarchitects we determined that all IA-32 and current generations
> > of Itanium microprocessors support this due to identifiable and
> > atomic global observation points for any store. This is mostly due to
> > the shared bus and single chipset."
>
> It's my understanding that AMD Opterons have a separate memory controller
> per socket; no shared bus and no single chipset (north bridge). They are
> also NUMA since some parts of the memory are attached to this CPU and some
> require CPU to CPU communication.

Yeah, and IBM does some NUMA with Intel Xeons, IIRC. That's why I've
been telling all along that lock_cmpxchg(&var, 42, 42) for loads is
the way to do SC on x86/IA32. ;-)

regards,
alexander.