[cpp-threads] SC for IRIW on Power Architecture

[Alexander Terekhov]

(was: [cpp-threads] Alternatives to SC)

On 1/16/07, Raul Silvera <rauls at ca.ibm.com> wrote:
[...]
> In any case, my original point was not so much about this example, but
> about consecutive atomic loads. In the IRIW case, you need a sync between
> the two loads on P3 and on P4.

IRIW case:

P1: x = 1;
P2: y = 1;
P3: r1 = x; r2 = y;
P4: r3 = y; r4 = x;

Let's add syncs...

P1: x = 1;
P2: y = 1;
P3: r1 = x; sync(); r2 = y;
P4: r3 = y; sync(); r4 = x;

Would that be SC according to Power Architecture specification? I
don't think so.

P1: x = 1;
P2: y = 1;
P3: do r1 = LR(&x) while !SC(&x, r1); do r2 = LR(&y) while !SC(&y, r2);
P4: do r3 = LR(&y) while !SC(&y, r3); do r4 = LR(&x) while !SC(&x, r4);

That will be SC (if paranoid you can add isyncs in between loops).

Please prove me wrong. :-)

regards,
alexander.