[cpp-threads] SC for IRIW on Power Architecture

[Doug Lea]

> IRIW case:
> 
> P1: x = 1;
> P2: y = 1;
> P3: r1 = x; r2 = y;
> P4: r3 = y; r4 = x;
> 
> Let's add syncs...
> 
> P1: x = 1;
> P2: y = 1;
> P3: r1 = x; sync(); r2 = y;
> P4: r3 = y; sync(); r4 = x;
> 
> Would that be SC according to Power Architecture specification? I
> don't think so.
> 

I agree that it is not SC according to section 1.7 (mainly) of book 2
of current PPC spec
(http://www-128.ibm.com/developerworks/eserver/library/es-archguide-v2.html)
And people I asked at IBM agree with me. It is possible to twist some
unintended meaning into a few statements in the spec to conclude that this
is SC, but they will hopefully be fixing/clarifying this.

Similar constructions on x86 are also not uncontroversially guaranteed SC in
current Intel and AMD specs. And similarly for some other processors.

As I mentioned in another post, processor implementations are often
stronger than their own specs require, so it is not necessarily
the case that IRIW non-SC-ness actually occur. (And it is extremely
difficult to test for unless you have a machine around to do nothing
but check for it for days, weeks or months.)

And again, all this comprises the practical reason for preferring
CCCC model for strong-atomics/volatiles. (In addition to conceptual
reasons I've posted.) It's pretty clear to me that all multiprocessors
supporting C++ (and/or Java) conform to CCCC.


> P1: x = 1;
> P2: y = 1;
> P3: do r1 = LR(&x) while !SC(&x, r1); do r2 = LR(&y) while !SC(&y, r2);
> P4: do r3 = LR(&y) while !SC(&y, r3); do r4 = LR(&x) while !SC(&x, r4);
> 
> That will be SC (if paranoid you can add isyncs in between loops).
> 

Of course, no one is precluding that C++ support a "pedanticallySC"
mode for atomics (add this to the ordering enum :-) for people
who are willing to live with the horrible performance consequences
of such things. (In the likely event we revise the associated Java spec,
we would add such an operation.)

-Doug